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Verilog: User Defined Primitives (UDP) of D Flip Flop

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Verilog Code for User Defined Primitives of D Flip Flop

primitive D_FF(
    input clk, clear,
    output q, q+
    );
table 
//clk clear : q : q+ ;
  ?      1  : ? : 0 ; //asynchronous clear condition
  ?    (10) : ? : - ; //ignore -ve edge of clear
(10)     0  : 1 : 1 ; //toggle FF at -ve edge of clk
(10)     0  : 0 : 0 ;
(0?)     0  : ? : - ; //ignore +ve edge of clock


endtable 
endprimitive

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