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Verilog: JK Flip Flop Behavioral Modelling using If Else Statement with Testbench Code

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Verilog Code for JK Flip Flop Behavioral Modelling using If Else with Testbench Code

module JK_FF(
    input J,K,clock,reset,
    output q, qb
    );
reg q, qb; 

always @ (posedge (clock))
    begin  
        if (reset)
            begin
               q <= 0;
               qb <=1;
            end    
        else
            begin
               if (J != K)
                    begin
                    q <= J;
                    qb <= K;
                    end 
               else if (J == 1 && K == 1) 
                    begin 
                    q <= 1'bZ; 
                    qb <= 1'bZ; 
                    end 
            end
 
end   
endmodule
//Testbench code for JK Flip Flop Behavioral Modelling using If Else Statement
initial begin
// Initialize Inputs 
J = 0; K = 0; 
// Wait 100 ns for global reset to finish 
#100;
// Add stimulus here 
#100; J=0; K=1; 
#100; J=1; K=0; 
#100; J=1; K=1; 
end
initial begin 
#100 
$monitor(“clock=%b, reset=%b, J=%b, K=%b, q=%b, qb=%b”,
clock, reset, J, K, q, qb); 
end 
endmodule

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