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Verilog: 2 Bit Counter Behavioral Modelling using If Else Statement

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Verilog Code for 2 Bit Counter Behavioral Modelling using If Else Statement 

module 2_bit_Count(
    input clock, reset,
    output [1:0]dout
    );
reg [1:0]dout; 
initial dout = 0;
 
always @ (posedge (clock))
   begin 
        if (reset) 
            dout <= 0; 
        else 
            dout <= dout + 1; 
   end 
endmodule

Xillinx Output:

2 Bit Counter using If Else Behavioral Modelling
2 Bit Counter using If Else Behavioral Modelling
 

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