Verilog: 1 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code

Verilog Code for 1 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code

module 1_Mag_Comp(
    input a,b,
    output equal, greater, lower 
    );
reg greater, equal, lower; 
initial greater = 0, equal = 0, lower = 0; 
always @ (a or b)
    begin  
        if (a < b)
            begin
            greater = 0; equal = 0; lower = 1;
            end   
        else if (a == b)
            begin
            greater = 0; equal = 1; lower = 0;
            end
        else
            begin
            greater = 1; equal = 0; lower = 0;
            end
end   
endmodule
//Testbench code for 1 Bit Magnitude Comparator Behavioral Modelling using If Else Statement
initial begin
// Initialize Inputs 
a = 0; b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; a = 0; b = 1;
#100; a = 1; b = 0;
#100; a = 1; b = 1; 
end
initial begin 
#100 
$monitor(“a = %b, b = %b, lower = %b, greater = %b, equal = %b”, a, b, lower, greater, equal); 
end 
endmodule 

Xillinx Output:

1 Bit Magnitude Comparator Verilog Response