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Verilog: D Flip Flop Behavioral Modelling using If Else Statement with Testbench Code

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Verilog Code for D Flip Flop Behavioral Modelling using If Else with Testbench Code

module D_FF(
    input D,clock,reset,
    output q, qb
    );
reg q, qb; 

always @ (posedge (clock))
    begin  
        if (reset)
               q <= 0;
        else
               q <= D;

    end   
endmodule
//Testbench code for D Flip Flop Behavioral Modelling using If Else Statement
initial begin
// Initialize Inputs 
D = 0; 
// Wait 100 ns for global reset to finish 
#100;
// Add stimulus here 
#100; D=1; 
#100; D=0;  
end
initial begin 
#100 
$monitor(“clock=%b, reset=%b, D=%b, q=%b, qb=%b”,
clock, reset, D, q, qb); 
end 
endmodule

Xillinx Output:
 
Verilog Code for D Flip Flop Behavioral Modelling using If Else with Testbench Code
D Flip Flop Verilog Code Xilinx Response

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