Verilog: 2 to 4 Decoder Behavioral Modelling using Case Statement with Testbench Code

Verilog Code for 2 to 4 Decoder Behavioral Modelling using Case Statement with Testbench Code

module 2_4_DEC(
    input [1:0]din,
    output [3:0]dout  
    );
reg [3:0]dout; 
always @ (din) 
case (din)
    0 : dout[0] = 1; 
    1 : dout[1] = 1; 
    2 : dout[2] = 1; 
    3 : dout[3] = 1; 
    default : dout = 4’bxxxx;
endcase 
endmodule
//Testbench code for 2 to 4 Decoder Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; din=0; 
#100; din=1; 
#100; din=2; 
#100; din=3;
end
initial begin 
#100 
$monitor(“din=%b, dout=%b”, din, dout); 
end 
endmodule 

Xillinx Output:

2 to 4 Decoder Behavioral Modelling Response