Latest Post

Ads

Verilog: User Defined Primitives (UDP) of OR Gate

-

Verilog Code for User Defined Primitives of OR Gate 

primitive udp_or(
    input a, b,
    output c
    );
table 
//a b : c
 1 ? : 1;
 ? 1 : 1;
 0 0 : 0;
 0 x : x;
 x 0 : x;

endtable 
endprimitive

Also See:

List of Verilog Programs

Comments

Post a Comment

Ads

Popular posts from this blog

VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench

-
Image
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs                              d = 1;                              s0 = 0;                              s1 = 0;                              // Wait 100 ns for global reset to finish                              #100;                   
Read more

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

-
Image
module bcd_ex3_Dataflow(     input a,     input b,     input c,     input d,     output w,     output x,     output y,     output z     ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd(     input w,     input x,     input y,     input z,     output a,     output b,     output c,     output d     ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Read more

VLSI: 2 Bit Magnitude Comparator Dataflow Modelling

-
Image
module mag_comp2bit(     input a0,     input a1,     input b0,     input b1,     output p,   // p = (a < b)     output r,     // r = (a > b)     output q     // q = (a = b)     ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule
Read more

1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench

-
Image
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module   demux_1_to_4(       input   d,       input   s0,       input   s1,       output   y0,       output   y1,       output   y2,       output   y3     ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial  begin // Initialize Inputs           d = 1;           s0 = 0;           s1 = 0; // Wait 100 ns for global reset to finish        #100; // Add stimulus here      #100;d = 1;s0 = 1;s1 = 0;      #100;d = 1;s0 = 0;s1 = 1;      #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of  Verilog Programming
Read more

Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench

-
Image
Verilog Code for Full Subtractor Structural/Gate Level Modelling module  full_sub(borrow,diff,a,b,c); output  borrow,diff; input  a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial  begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of  Verilog Programming
Read more