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Verilog: User Defined Primitives (UDP) of OR Gate

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Verilog Code for User Defined Primitives of OR Gate 

primitive udp_or(
    input a, b,
    output c
    );
table 
//a b : c
 1 ? : 1;
 ? 1 : 1;
 0 0 : 0;
 0 x : x;
 x 0 : x;

endtable 
endprimitive

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