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Verilog: BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement

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Verilog Code for BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement 

module bcd_Count(
    input clock, reset,
    output [3:0]dout
    );
reg [3:0]dout; 
initial dout = 0;
 
always @ (posedge (clock))
   begin 
        if (reset) 
            dout <= 0; 
        else if (dout <= 9) 
            dout <= dout + 1; 
        else if (dout == 9) 
            dout <= 0;
   end 
endmodule

Xillinx Output:

Verilog Code for BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement
BCD Counter Behavioral Modelling Response
 

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List of Verilog Programs

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