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Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling with Testbench Code

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Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling using Case Statement with Testbench Code

module pri_Enc(
    input [7:0]din,
    output [7:0]dout,
    );
reg [7:0]dout; 
 
always @ (din)
    case (din) 
    8’b 1xxx xxxx : dout = 7; 
    8’b x1xx xxxx : dout = 6; 
    8’b xx1x xxxx : dout = 5; 
    8’b xxx1 xxxx : dout = 4; 
    8’b xxxx 1xxx : dout = 3; 
    8’b xxxx x1xx : dout = 2; 
    8’b xxxx xx1x : dout = 1; 
    8’b xxxx xxx1 : dout = 0; 
    default : dout = 3’bxxx; 
    endcase
endmodule
//Testbench code for 8 to 3 Priority Encoder Behavioral Modelling 
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100 din=0;
#100 din=1; 
#100 din=2; 
#100 din=7; 
#100 din=8; 
#100 din=11; 
#100 din=42; 
#100 din=64; 
#100 din=32; 
#100 din=10;

end
initial begin 
#100 
$monitor(“din = %b, dout = %b”, din, dout); 
end 
endmodule

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