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Verilog: Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code

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Verilog Code for Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code

module Gry_Bin(
    input [3:0]din,
    output [3:0]dout
    );
reg [3:0]dout; 

always @ (din)
    begin  
        case (din)
           0 : dout = 0; 
           1 : dout = 1;
           2 : dout = 3; 
           3 : dout = 2; 
           4 : dout = 7; 
           5 : dout = 6; 
           6 : dout = 4; 
           7 : dout = 5; 
           8 : dout = 15; 
           9 : dout = 14; 
           10 : dout = 12; 
           11 : dout = 13; 
           12 : dout = 8; 
           13 : dout = 9; 
           14 : dout = 11; 
           15 : dout = 10; 
           default: dout = 4’b xxxx;   
        endcase
end   
endmodule
//Testbench code for Gray to Binary Converter Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish#100;
// Add stimulus here 
#100; din = 4;
#100; din = 15;
#100; din = 8; 
end
initial begin 
#100 
$monitor(“din = %b, dout = %b, din, dout); 
end 
endmodule

Xillinx Output:

Verilog Code for Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code
Gray to Binary Converter Verilog Code Behavioral Modelling

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