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Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code

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Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code

module 4_bit_Sub(
    input [3:0]a,b,
    input bin, 
    output [3:0]diff,
    output bout 
    );
reg [3:0]diff; 
reg bout; 
 
always @ (a or b or bin)
   assign {bout,diff}= (~a) + b + bin;
endmodule
//Testbench code for 4 Bit Full Subtractor Behavioral Modelling 
initial begin
// Initialize Inputs 
a = 0; b = 0; bin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100 a=4; b=9; bin=1; 
#100 a=15; b=5; bin=1; 
#100 a=7; b=5; bin=0; 
#100 a=6; b=10; bin=1;  
end
initial begin 
#100 
$monitor(“a = %b, b = %b, bin = %b, diff = %b, bout = %b”, a, b, bin, diff, bout); 
end 
endmodule

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