Verilog: 8 to 3 Encoder Behavioral Modelling using Case Statement with Testbench Code

Verilog Code for 8 to 3 Encoder Behavioral Modelling using Case Statement with Testbench Code

module 8_3_ENC(
    input [7:0]din,
    output [2:0]dout  
    );
reg [1:0]dout; 
always @ (din) 
case (din)
    1 : dout[0] = 0; 
    2 : dout[1] = 1; 
    4 : dout[2] = 2; 
    8 : dout[3] = 3; 
    16 : dout[4] = 4; 
    32 : dout[5] = 5; 
    64 : dout[6] = 6; 
    128 : dout[7] = 7; 
    default : dout = 3’bxxx;
endcase 
endmodule
//Testbench code for 3 to 8 Decoder Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; din=0; 
#100; din=1; 
#100; din=2; 
#100; din=4;
#100; din=8; 
#100; din=16; 
#100; din=32; 
#100; din=128;  
end
initial begin 
#100 
$monitor(“din=%b, dout=%b”, din, dout); 
end 
endmodule 

Xillinx Output:

8 - 3 Encoder Verilog Code Response