Verilog: T Flip Flop Behavioral Modelling using If Else Statement with Testbench Code

Verilog Code for T Flip Flop Behavioral Modelling using If Else with Testbench Code

module T_FF(
    input T,clock,reset,
    output q, qb
    );
reg q, qb; 

always @ (posedge (clock))
    begin  
        if (reset)
               q <= 0;
        else
               begin 
                   if (T)
                   q <= ~q;                
               end 
                

    end   
endmodule
//Testbench code for T Flip Flop Behavioral Modelling using If Else Statement
initial begin
// Initialize Inputs 
T = 0; clock = 0; reset = 0;
// Wait 100 ns for global reset to finish 
#100;
// Add stimulus here 
#100; T=1; 
#100; T=0;  
end
initial begin 
#100 
$monitor(“clock=%b, reset=%b, T=%b, q=%b, qb=%b”,
clock, reset, T, q, qb); 
end 
endmodule 

Xillinx Output:

T Flip Flop Verilog Code Behavioral Modelling