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Verilog: User Defined Primitives (UDP) of D Flip Flop
Verilog Code for User Defined Primitives of D Flip Flop primitive D_FF( input clk, clear , output q, q+ ); table //clk clear : q : q+ ; ? 1 : ? : 0 ; //asynchronous clear condition ? (10) : ? : - ; //ignore -ve edge of clear (10) 0 : 1 : 1 ; //toggle FF at -ve edge of clk (10) 0 : 0 : 0 ; (0?) 0 : ? : - ; //ignore +ve edge of clock endtable endprimitive Also See: List of Verilog Programs
Verilog: User Defined Primitives (UDP) of OR Gate
Verilog Code for User Defined Primitives of OR Gate primitive udp_or( input a, b , output c ); table //a b : c 1 ? : 1; ? 1 : 1; 0 0 : 0; 0 x : x; x 0 : x; endtable endprimitive Also See: List of Verilog Programs
Verilog: User Defined Premitives (UDP) of AND Gate
Verilog Code for User Defined Primitives of AND Gate primitive udp_and( input a, b , output out ); table //a b : out -------------- 0 0 : 0; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive Also See: List of Verilog Programs
Verilog: BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement
Verilog Code for BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement module bcd_Count( input clock, reset, output [3:0]dout ); reg [3:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else if (dout <= 9) dout <= dout + 1; else if (dout == 9) dout <= 0; end endmodule Xillinx Output: BCD Counter Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: 4 Bit Full Adder Behavioral Modelling with Testbench Code
Verilog Code for 4 Bit Full Adder Behavioral Modelling with Testbench Code module 4_bit_Add( input [3:0]a,b, input cin, output [3:0]sum, output cout ); reg [3:0]sum; reg cout; always @ (a or b or cin) assign {cout,sum}= a + b + cin; endmodule //Testbench code for 4 Bit Full Adder Behavioral Modelling initial begin // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 a=4; b=9; cin=1; #100 a=15; b=5; cin=1; #100 a=7; b=5; cin=0; #100 a=6; b=10; cin=1; end initial begin #100 $monitor (“ a = %b, b = %b, cin = %b, sum = %b, cout = %b”, a, b, cin, sum, cout); end endmodule Xillinx Output: 4 Bit Full Adder Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: 2 Bit Counter Behavioral Modelling using If Else Statement
Verilog Code for 2 Bit Counter Behavioral Modelling using If Else Statement module 2_bit_Count( input clock, reset, output [1:0]dout ); reg [1:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else dout <= dout + 1; end endmodule Xillinx Output: 2 Bit Counter using If Else Behavioral Modelling Also See: List of Verilog Programs
Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling with Testbench Code
Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling using Case Statement with Testbench Code module pri_Enc( input [7:0]din, output [7:0]dout, ); reg [7:0]dout; always @ (din) case (din) 8’b 1xxx xxxx : dout = 7; 8’b x1xx xxxx : dout = 6; 8’b xx1x xxxx : dout = 5; 8’b xxx1 xxxx : dout = 4; 8’b xxxx 1xxx : dout = 3; 8’b xxxx x1xx : dout = 2; 8’b xxxx xx1x : dout = 1; 8’b xxxx xxx1 : dout = 0; default : dout = 3’bxxx; endcase endmodule //Testbench code for 8 to 3 Priority Encoder Behavioral Modelling initial begin // Initialize Inputs din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 din...
Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code
Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code module 4_bit_Sub( input [3:0]a,b, input bin, output [3:0]diff, output bout ); reg [3:0]diff; reg bout; always @ (a or b or bin) assign {bout,diff}= (~a) + b + bin; endmodule //Testbench code for 4 Bit Full Subtractor Behavioral Modelling initial begin // Initialize Inputs a = 0; b = 0; bin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 a=4; b=9; bin=1; #100 a=15; b=5; bin=1; #100 a=7; b=5; bin=0; #100 a=6; b=10; bin=1; end initial begin #100 $monitor (“ a = %b, b = %b, bin = %b, diff = %b, bout = %b”, a, b, bin, diff, bout); end endmodule Also See: List of Verilog Programs
Verilog: 3 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for 3 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code module 3_Mag_Comp( input [2:0]a,b, output equal, greater, lower ); reg greater, equal, lower; initial greater = 0, equal = 0, lower = 0; always @ (a or b) begin if (a < b) begin greater = 0; equal = 0; lower = 1; end else if (a == b) begin greater = 0; equal = 1; lower = 0; end else ...
Verilog: T Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for T Flip Flop Behavioral Modelling using If Else with Testbench Code module T_FF( input T,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) q <= 0; else begin if (T) q <= ~q; end ...
Verilog: D Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for D Flip Flop Behavioral Modelling using If Else with Testbench Code module D_FF( input D,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) q <= 0; else q <= D; end endmodule //Testbench code for D Flip Flop Behavioral Modelling using If Else Statement initial begin // Initialize Inputs D = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; D=1; #100; D=0; end initial begin #100 $monitor (“ clock=%b, reset=%b, D=%b, q=%b, qb=%b”, clock, reset, D, q, qb); end endmodule Xillinx Outp...
Verilog: JK Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for JK Flip Flop Behavioral Modelling using If Else with Testbench Code module JK_FF( input J,K,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) begin q <= 0; qb <=1; end else begin if (J != K) begin ...
Verilog: Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code
Verilog Code for Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code module Gry_Bin( input [3:0]din, output [3:0]dout ); reg [3:0]dout; always @ (din) begin case (din) 0 : dout = 0; 1 : dout = 1; 2 : dout = 3; 3 : dout = 2; 4 : dout = 7; 5 : dout = 6; 6 : dout = 4; 7 : dout = 5; 8 : dout = 15; ...
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VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Verilog: 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code
Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code module 4_2_ENC( input [3:0]din, output [1:0]dout ); reg [1:0]dout; always @ (din) case (din) 1 : dout[0] = 0; 2 : dout[1] = 1; 4 : dout[2] = 2; 8 : dout[3] = 3; default : dout = 2’bxx; endcase endmodule //Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement initial begin // Initialize Inputs din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; din=1; #100; din=2; #100; din=4; #100; din=8; end initial begin #100 $monitor (“ din=%b, dout=%b”, din, dout); end endmodule Xillinx Output: 4 - 2 Encoder Behavioral Modelling Verilog Response
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
VLSI: 8-3 Encoder Dataflow Modelling with Testbench
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3( input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, output q0, output q1, output q2 ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin ...