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Verilog: User Defined Primitives (UDP) of D Flip Flop
Verilog Code for User Defined Primitives of D Flip Flop primitive D_FF( input clk, clear , output q, q+ ); table //clk clear : q : q+ ; ? 1 : ? : 0 ; //asynchronous clear condition ? (10) : ? : - ; //ignore -ve edge of clear (10) 0 : 1 : 1 ; //toggle FF at -ve edge of clk (10) 0 : 0 : 0 ; (0?) 0 : ? : - ; //ignore +ve edge of clock endtable endprimitive Also See: List of Verilog Programs
Verilog: User Defined Primitives (UDP) of OR Gate
Verilog Code for User Defined Primitives of OR Gate primitive udp_or( input a, b , output c ); table //a b : c 1 ? : 1; ? 1 : 1; 0 0 : 0; 0 x : x; x 0 : x; endtable endprimitive Also See: List of Verilog Programs
Verilog: User Defined Premitives (UDP) of AND Gate
Verilog Code for User Defined Primitives of AND Gate primitive udp_and( input a, b , output out ); table //a b : out -------------- 0 0 : 0; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive Also See: List of Verilog Programs
Verilog: BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement
Verilog Code for BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement module bcd_Count( input clock, reset, output [3:0]dout ); reg [3:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else if (dout <= 9) dout <= dout + 1; else if (dout == 9) dout <= 0; end endmodule Xillinx Output: BCD Counter Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: 4 Bit Full Adder Behavioral Modelling with Testbench Code
Verilog Code for 4 Bit Full Adder Behavioral Modelling with Testbench Code module 4_bit_Add( input [3:0]a,b, input cin, output [3:0]sum, output cout ); reg [3:0]sum; reg cout; always @ (a or b or cin) assign {cout,sum}= a + b + cin; endmodule //Testbench code for 4 Bit Full Adder Behavioral Modelling initial begin // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 a=4; b=9; cin=1; #100 a=15; b=5; cin=1; #100 a=7; b=5; cin=0; #100 a=6; b=10; cin=1; end initial begin #100 $monitor (“ a = %b, b = %b, cin = %b, sum = %b, cout = %b”, a, b, cin, sum, cout); end endmodule Xillinx Output: 4 Bit Full Adder Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: 2 Bit Counter Behavioral Modelling using If Else Statement
Verilog Code for 2 Bit Counter Behavioral Modelling using If Else Statement module 2_bit_Count( input clock, reset, output [1:0]dout ); reg [1:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else dout <= dout + 1; end endmodule Xillinx Output: 2 Bit Counter using If Else Behavioral Modelling Also See: List of Verilog Programs
Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling with Testbench Code
Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling using Case Statement with Testbench Code module pri_Enc( input [7:0]din, output [7:0]dout, ); reg [7:0]dout; always @ (din) case (din) 8’b 1xxx xxxx : dout = 7; 8’b x1xx xxxx : dout = 6; 8’b xx1x xxxx : dout = 5; 8’b xxx1 xxxx : dout = 4; 8’b xxxx 1xxx : dout = 3; 8’b xxxx x1xx : dout = 2; 8’b xxxx xx1x : dout = 1; 8’b xxxx xxx1 : dout = 0; default : dout = 3’bxxx; endcase endmodule //Testbench code for 8 to 3 Priority Encoder Behavioral Modelling initial begin // Initialize Inputs din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 din...
Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code
Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code module 4_bit_Sub( input [3:0]a,b, input bin, output [3:0]diff, output bout ); reg [3:0]diff; reg bout; always @ (a or b or bin) assign {bout,diff}= (~a) + b + bin; endmodule //Testbench code for 4 Bit Full Subtractor Behavioral Modelling initial begin // Initialize Inputs a = 0; b = 0; bin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100 a=4; b=9; bin=1; #100 a=15; b=5; bin=1; #100 a=7; b=5; bin=0; #100 a=6; b=10; bin=1; end initial begin #100 $monitor (“ a = %b, b = %b, bin = %b, diff = %b, bout = %b”, a, b, bin, diff, bout); end endmodule Also See: List of Verilog Programs
Verilog: 3 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for 3 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code module 3_Mag_Comp( input [2:0]a,b, output equal, greater, lower ); reg greater, equal, lower; initial greater = 0, equal = 0, lower = 0; always @ (a or b) begin if (a < b) begin greater = 0; equal = 0; lower = 1; end else if (a == b) begin greater = 0; equal = 1; lower = 0; end else ...
Verilog: T Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for T Flip Flop Behavioral Modelling using If Else with Testbench Code module T_FF( input T,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) q <= 0; else begin if (T) q <= ~q; end ...
Verilog: D Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for D Flip Flop Behavioral Modelling using If Else with Testbench Code module D_FF( input D,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) q <= 0; else q <= D; end endmodule //Testbench code for D Flip Flop Behavioral Modelling using If Else Statement initial begin // Initialize Inputs D = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; D=1; #100; D=0; end initial begin #100 $monitor (“ clock=%b, reset=%b, D=%b, q=%b, qb=%b”, clock, reset, D, q, qb); end endmodule Xillinx Outp...
Verilog: JK Flip Flop Behavioral Modelling using If Else Statement with Testbench Code
Verilog Code for JK Flip Flop Behavioral Modelling using If Else with Testbench Code module JK_FF( input J,K,clock,reset, output q, qb ); reg q, qb; always @ (posedge (clock)) begin if (reset) begin q <= 0; qb <=1; end else begin if (J != K) begin ...
Verilog: Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code
Verilog Code for Gray to Binary Converter Behavioral Modelling using Case Statement with Testbench Code module Gry_Bin( input [3:0]din, output [3:0]dout ); reg [3:0]dout; always @ (din) begin case (din) 0 : dout = 0; 1 : dout = 1; 2 : dout = 3; 3 : dout = 2; 4 : dout = 7; 5 : dout = 6; 6 : dout = 4; 7 : dout = 5; 8 : dout = 15; ...
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VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
Verilog: 8 to 1 Multiplexer (8-1 MUX) Dataflow Modelling with Testbench Code
Verilog Code for 8 to 1 Multiplexer Dataflow Modelling module mux_8to1( input a, input b, input c, input D0, input D1, input D2, input D3, input D4, input D5, input D6, input D7, output out, ); module m81( output out, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2); assign S1bar=~S1; assign S0bar=~S0; assign S2bar=~S2; assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & S0) | (D2 & S2bar & S1 & S0bar) + (D3 & S2bar & S1 & S0) + (D4 & S2 & S1bar & S0bar) + (D5 & S2 & S1bar & S0) + (D6 & S2 & S1 & S0bar) + (D7 & S2 & S1 & S0); endmodule //Testbench code for 8-1 MUX Dataflow Modelling initial begin // Initialize Inputs a= 0;b = 0;c = 0;D0 = 1;D1 = 0;D2 = 0;D3 = 0;D4 = 0;D5 = 0;D6 = 0;D7 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1;d0 = ...
VLSI: Half Subtractor and Full Subtractor Gate Level Modelling
Half Subtractor: Verilog Module Code: module half_subtractor ( input a, input b, output diff output borr ); wire x; xor (diff,a,b); not (x,a); and (borr,x,b); endmodule Full Subtractor: Verilog Module Code: module full_subtractor ( input a, input b, input c, output diff output borr ); wire x,n2,z,n1; xor s1(x,a,b); not s3(n2,x); not s4(n1,c); and s5(y,n1,b); xor s2(diff,a,x); and s6(z,n2,a); or (borr,y,z); endmodule