Stellar Coding - Verilog, Filter Design and more..

Verilog Code for User Defined Primitives of D Flip Flop primitive D_FF(      input clk, clear ,      output q, q+     ); table  //clk clear : q : q+ ; ? 1 : ? : 0 ; //asynchronous clear condition ? (10) : ? : - ; //ignore -ve edge of clear (10) 0 : 1 : 1 ; //toggle FF at -ve edge of clk (10) 0 : 0 : 0 ; (0?) 0 : ? : - ; //ignore +ve edge of clock endtable  endprimitive Also See: List of Verilog Programs

Verilog Code for User Defined Primitives of OR Gate primitive udp_or(      input a, b ,      output c     ); table  //a b : c 1 ? : 1; ? 1 : 1; 0 0 : 0; 0 x : x; x 0 : x; endtable  endprimitive Also See: List of Verilog Programs

Verilog Code for User Defined Primitives of AND Gate primitive udp_and(      input a, b ,      output out     ); table  //a b : out  --------------    0 0 : 0;    0 1 : 0;    1 0 : 0;    1 1 : 1;  endtable  endprimitive Also See: List of Verilog Programs

Verilog Code for BCD Counter (Mod 10 Counter) Behavioral Modelling using If Else Statement module bcd_Count(      input clock, reset,      output [3:0]dout     ); reg [3:0]dout;  initial dout = 0;   always @ (posedge (clock))    begin            if (reset)                 dout <= 0;            else if (dout <= 9)               dout <= dout + 1;           else if (dout == 9)                dout <= 0;    end endmodule Xillinx Output: BCD Counter Behavioral Modelling Response   Also See: List of Verilog Programs

Verilog Code for 4 Bit Counter Behavioral Modelling using If Else Statement module 4_bit_Count(      input clock, reset,      output [3:0]dout     ); reg [3:0]dout;  initial dout = 0;   always @ (posedge (clock))    begin            if (reset)                 dout <= 0;            else                dout <= dout + 1;     end endmodule Xillinx Output: 4 Bit Counter Behavioral Modelling Response   Also See: List of Verilog Programs

Verilog Code for 4 Bit Full Adder Behavioral Modelling with Testbench Code module 4_bit_Add(      input [3:0]a,b,     input cin,      output [3:0]sum,     output cout     ); reg [3:0]sum;  reg cout;   always @ (a or b or cin)    assign {cout,sum}= a + b + cin; endmodule //Testbench code for 4 Bit Full Adder Behavioral Modelling initial  begin // Initialize Inputs   a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100 a=4; b=9; cin=1;  #100 a=15; b=5; cin=1;  #100 a=7; b=5; cin=0;  #100 a=6; b=10; cin=1;  end initial begin  #100   $monitor (“ a = %b, b = %b, cin = %b, sum = %b, cout = %b”, a, b, cin, sum, cout);  end  endmodule Xillinx Output: 4 Bit Full Adder Behavioral Modelling Response Also See: List of Verilog Programs

Verilog Code for 2 Bit Counter Behavioral Modelling using If Else Statement module 2_bit_Count(      input clock, reset,      output [1:0]dout     ); reg [1:0]dout;  initial dout = 0;   always @ (posedge (clock))    begin            if (reset)                 dout <= 0;            else                dout <= dout + 1;     end endmodule Xillinx Output: 2 Bit Counter using If Else Behavioral Modelling   Also See: List of Verilog Programs

Verilog Code for 8 to 3 Priority Encoder Behavioral Modelling using Case Statement with Testbench Code module pri_Enc(      input [7:0]din,      output [7:0]dout,     ); reg [7:0]dout;   always @ (din)     case (din)     8’b 1xxx xxxx : dout = 7;       8’b x1xx xxxx : dout = 6;       8’b xx1x xxxx : dout = 5;       8’b xxx1 xxxx : dout = 4;       8’b xxxx 1xxx : dout = 3;       8’b xxxx x1xx : dout = 2;       8’b xxxx xx1x : dout = 1;      8’b xxxx xxx1 : dout = 0;       default : dout = 3’bxxx;      endcase endmodule //Testbench code for 8 to 3 Priority Encoder Behavioral Modelling initial  begin // Initialize Inputs   din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100 din...

Verilog Code for 4 Bit Full Subtractor Behavioral Modelling with Testbench Code module 4_bit_Sub(      input [3:0]a,b,     input bin,      output [3:0]diff,     output bout     ); reg [3:0]diff;  reg bout;   always @ (a or b or bin)    assign {bout,diff}= (~a) + b + bin; endmodule //Testbench code for 4 Bit Full Subtractor Behavioral Modelling initial  begin // Initialize Inputs   a = 0; b = 0; bin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100 a=4; b=9; bin=1;  #100 a=15; b=5; bin=1;  #100 a=7; b=5; bin=0;  #100 a=6; b=10; bin=1;  end initial begin  #100   $monitor (“ a = %b, b = %b, bin = %b, diff = %b, bout = %b”, a, b, bin, diff, bout);  end  endmodule Also See: List of Verilog Programs

Verilog Code for 3 Bit Magnitude Comparator Behavioral Modelling using If Else Statement with Testbench Code module 3_Mag_Comp(      input [2:0]a,b,      output equal, greater, lower     ); reg greater, equal, lower;  initial greater = 0, equal = 0, lower = 0; always @ (a or b)      begin            if (a < b)               begin               greater = 0; equal = 0; lower = 1;                end             else if (a == b)               begin               greater = 0; equal = 1; lower = 0;               end          else    ...

Verilog Code for T Flip Flop Behavioral Modelling using If Else with Testbench Code module T_FF(      input T,clock,reset,      output q, qb     ); reg q, qb;  always @ (posedge (clock))      begin           if (reset)                   q <= 0;          else                   begin                        if (T)                        q <= ~q;                                       end                     ...

Verilog Code for D Flip Flop Behavioral Modelling using If Else with Testbench Code module D_FF(      input D,clock,reset,      output q, qb     ); reg q, qb;  always @ (posedge (clock))      begin           if (reset)                   q <= 0;          else                   q <= D;      end   endmodule //Testbench code for D Flip Flop Behavioral Modelling using If Else Statement initial  begin // Initialize Inputs   D = 0;  // Wait 100 ns for global reset to finish   #100; // Add stimulus here   #100; D=1;  #100; D=0;  end initial begin  #100   $monitor (“ clock=%b, reset=%b, D=%b, q=%b, qb=%b”, clock, reset, D, q, qb);  end  endmodule Xillinx Outp...

Verilog Code for JK Flip Flop Behavioral Modelling using If Else with Testbench Code module JK_FF(      input J,K,clock,reset,      output q, qb     ); reg q, qb;  always @ (posedge (clock))      begin           if (reset)               begin                   q <= 0;                   qb <=1;               end             else               begin                   if (J != K)                         begin              ...