Latest Post
Alien Stones from Space !!
- Get link
- X
- Other Apps
Many people have some unique interesting hobbies, one of that is collection of heavenly stones (Meteorite Stones). We can also find a museum at Chicago called "Garden of Heaven". Garden of Heaven is museum of meteor stones collected from different places and different continents. For some this is business, to hunt for meteor stones and sell at very high price.
Most of the meteors belong to Asteroid belt between orbits of Mars and Jupiter, but few of them belonged to Moon and Mars!! Sometimes when a massive Asteroid hits surface of Mars, small surface objects on mars bounces and leaves gravity of Mars. When such objects are captured by Earth's gravity, they enter into Earth's atmosphere. Similarly different objects arrive from Moon. This is possible because Mars has weak gravity and moon being closest to Earth with very weak gravity.
Mechanic Farmer is a well known name of Meteorite hunter.
Few heavenly rocks found are:
1. E-Mevak found in 1922 in Chile (Opening particles).
2. Aahumda found in Mexico in 1909, kept in Garden of Heaven museum, Chicago.
Axtel found in Texas in 1943, it is Carbonesius Contract.
Martian rock named Sapt Al Uhaymir 008 found in 1999 from Oman.
5. Another Martian Meteorite rock Indark found from Azerbaijan in 1958.
6. Park forest found in Illinois in USA in 2003.
7. Homstick found in 1857.
8. Crab Orchid found in 1887, Tennesse, USA.
Many meteorite rocks found in Antarctica can be easily recognized as meteor rocks because these are found above the snowbed. Antarctica and Arctic region are hot favourite destinations for meteor rock hunting.
These rocks are rated in market depending upon how old is the rock, what the rock is made up of, weight, origin of rock (moon,mars or any Asteroid),etc.
There are passionate buyers who buy these rocks as a hobby or for their museum collection.
- Get link
- X
- Other Apps
Popular posts from this blog
Samir Palnitkar Solution Manual Free Download PDF of Verilog HDL
This is a solution guide to the exercises of the book "The Solution Manual of the Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar". Following are the Solutions to Solution Manual on Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar , exercises of all chapters in the book. Chapter 1 ----------------- No Exercises ---------------- Chapter 2 : Hierarchical Modeling Concepts Chapter 3 : Basic Concepts Chapter 4 : Modules and Ports Chapter 5: Gate-level Modeling Chapter 6 : Dataflow Modeling Chapter 7 : Behavioral Modeling Chapter 8 : Tasks and Functions Download Solution Manual: Click on this link (Mega.nz Link) [Solution Manual to Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar] Preview of Solution Manual: For Verilog Programs: Go to Index of Verilog Programming Tags: Verilog HDL solutio...
VLSI: 8-3 Encoder Dataflow Modelling with Testbench
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3( input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, output q0, output q1, output q2 ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin ...
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
VLSI: 3-8 Decoder Dataflow Modelling with Testbench
Verilog Code for 3-8 Decoder Dataflow Modelling module decoder3_to_8( input x, input y, input z, output d0, output d1, output d2, output d3, output d4, output d5, output d6, output d7 ); assign d0 = xn & yn & zn; assign d1 = xn & yn & z; assign d2 = xn & y & zn; assign d3 = xn & y & z; assign d4 = x & yn & z; assign d5 = x & yn & z; assign d6 = x & y & zn; assign d7 = x & y & z; assign xn = ~ x; assign yn = ~ y; assign zn = ~ z; endmodule //Testbench code for 3-8 Decoder Dataflow Modelling ...
Verilog: 4 to 1 Multiplexer Behavioral Modelling with Testbench Code
Verilog Code 4-1 Multiplexer Behavioral Modelling using Case Statement module Mux_4to1 ( input [3:0] i, input s1, s0, output out ); always @(i or s1 or s0) case({s1, s0}) 0 : out = i[0]; 1 : out = i[1]; 2 : out = i[2]; 3 : out = i[3]; default : out = 1’bx; endcase endmodule // test-bench initial begin i=1'b1010; s1=0; s0=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 s1 = 0; s0= 1; #100 s1 = 1; s0= 0; #100 s1 = 1; s0= 1; end

Comments
Post a Comment