Latest Post

Space Facts: Part 2 - Dark Matter, Comet 67P and Different types of Space Telescopes

-

1. Dark Matter:

Dark matter is made up of WIMP or AXION particles, WIMP means Weakly Intensive Massive Particles.

2. Comet: 67 P

67P/Churyumov Gerasimenkov comet takes 6.5 earth years to complete one revolution of solar system. Rosetta is the first satellite to reach comet's orbit. Rosetta is spacecraft from ESA (European Space Agency) which contained Rover and Orbiter. Comets generally come from Cloud of Urt or Kuiper Belt.


3. Space Telescopes and Observatories:

There are different types of space observatories made by different space organizations like NASA, ESA, JAXA, ROSCOSMO, CNSA, ISRO, etc.

 X-Ray: Chandra X-Ray Spacecraft
Gravity wave telescope:  BICEP 2
Microwave: Wisconsin Microwave Aniastropy Probe, Cosmic Microwave Background Explorer (COBE)
Gamma Ray,Neutrino observatory, Optical telescope, etc.

Comments

Post a Comment

Popular posts from this blog

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

-
Image
module bcd_ex3_Dataflow(     input a,     input b,     input c,     input d,     output w,     output x,     output y,     output z     ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd(     input w,     input x,     input y,     input z,     output a,     output b,     output c,     output d     ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Read more

VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench

-
Image
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs ...
Read more

VLSI: 8-3 Encoder Dataflow Modelling with Testbench

-
Image
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3(     input d0,     input d1,     input d2,     input d3,     input d4,     input d5,     input d6,     input d7,     output q0,     output q1,     output q2     ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin                         ...
Read more

VLSI: 4-1 MUX Dataflow Modelling with Testbench

-
Image
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin                              // Initialize Inputs                              a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;        ...
Read more

Verilog: 2 - 4 Decoder Structural/Gate Level Modelling with Testbench

-
Image
Verilog Code for 2-4 Decoder Structural/Gate Level Modelling 2-4 Line Decoder module  decoder_2_to_4(      input  a0,      input  a1,      output  d0,      output  d1,      output  d2,      output  d3     );                 not (an0,a0),(an1,a1);                 and (d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1); endmodule //Testbench code for 2-4 Decoder Structural/Gate Level Modelling initial  begin // Initialize Inputs a0 = 0;a1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a0=1;a1=0; #100; a0=0;a1=1; #100; a0=1;a1=1; end Output: Verilog 2-4 Decoder Response Other Verilog Programs: Go to Index of  Verilog Prog...
Read more