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Planets: Jupiter
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A look at some interesting facts of Jupiter:
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| Jupiter and Spacecraft Juno, Artist Image |
Jupiter is the largest planet of our solar system, so big that it can fit more than 1300 Earths inside it. Thick colorful clouds of deadly poisonous gases surround Jupiter. The quick spinning of the planet whips up the atmosphere, creating bands around the planet.
If you were to descend into Jupiter, thin cold atmosphere becomes thicker and hotter, gradually turning into a thick dark fog. In the blackness about 1000 Km down the pressure squeezes the atmosphere so hard that it turns into liquid. Center of Jupiter is made up of rocky core, slightly bigger than Earth but weighing about 20 times more than weight of Earth.
Surrounding the core is ocean of liquid hydrogen, about 1000 Km deep. Jupiter has many storms, some can be seen from Earth via telescope. The big red spot of Jupiter is the largest hurricane in our solar system. It's been ranging for 3 hundred years. Jupiter has strong magnetic field, you would weigh 2 and half times as much as you weigh on Earth.
Jupiter has many moons circling around it. Four of these moons are even bigger than Pluto. Galileo and Juno are famous spacecrafts sent to study Jupiter.
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