Latest Post

Space Facts: Part 9 - Quantum Fluctuations

-
Have you heard of Quantum Fluctuations?

It's a part of Quantum Physics. Quantum Fluctuations describe that even from void space matter can be generated. But for this to happen there are certain rules:
1. Matter appearing from void will have negligible mass.
2. Matter will appear for very less time and disappear again.
3. Heavy mass matter cannot be generated.

Now, assume that in empty space there is no form of positive energy, but energy is present in negative form. From this negative energy particles may be formed for very less amount of time and gives back energy to surrounding and disappears.
By Quantum Fluctuations particles like electrons can be created but not protons and neutrons. Einstein compared this principle with universe and gave his theory of Relativity.

How we find the age of Universe practically?

BICEP 1 and BICEP 2 are gravity wave telescopes located in Antarctica. BICEP 2 captured 13.7 billion years old gravity waves, which were the oldest waves ever captured by any telescope.
To know what are gravity waves Click Here.

Comments

Post a Comment

Popular posts from this blog

VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench

-
Image
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs ...
Read more

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

-
Image
module bcd_ex3_Dataflow(     input a,     input b,     input c,     input d,     output w,     output x,     output y,     output z     ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd(     input w,     input x,     input y,     input z,     output a,     output b,     output c,     output d     ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Read more

Verilog: 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code

-
Image
Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code module 4_2_ENC(      input [3:0]din,      output [1:0]dout      ); reg [1:0]dout; always @ (din) case (din)     1 : dout[0] = 0;      2 : dout[1] = 1;      4 : dout[2] = 2;      8 : dout[3] = 3;       default : dout = 2’bxx; endcase endmodule //Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100; din=1;  #100; din=2;  #100; din=4;  #100; din=8; end initial begin  #100   $monitor (“ din=%b, dout=%b”, din, dout);  end  endmodule Xillinx Output: 4 - 2 Encoder Behavioral Modelling Verilog Response
Read more

1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench

-
Image
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module   demux_1_to_4(       input   d,       input   s0,       input   s1,       output   y0,       output   y1,       output   y2,       output   y3     ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial  begin // Initialize Inputs           d = 1;           s0 = 0;           s1 = 0; // Wait 100 ns for global reset to finish        #100; // Add stimulus here      #100;d = 1;s0 = 1;s1 = 0;      #100;d = 1;s0 = ...
Read more

VLSI: 8-3 Encoder Dataflow Modelling with Testbench

-
Image
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3(     input d0,     input d1,     input d2,     input d3,     input d4,     input d5,     input d6,     input d7,     output q0,     output q1,     output q2     ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin                         ...
Read more