Latest Post

Space Facts: Part 6 - Apogee and Perigee

-

What is Apogee and Perigee ?

The point of orbit nearest to Earth is Perigee and farthest from Earth is called Apogee. Satellites sent from PSLV rockets follow this system as the speed of PSLV rockets is less than 11.2 Km/sec. Here spacecrafts have to change different orbits (also known as Orbit Maneuvers) around Earth to get speed of 11.2 Km/sec. By achieving speed higher than 11.2 Km/sec we spacecrafts can escape Earth's gravity, this velocity is called "Escape Velocity".
GSLV MK III rockets have speed 11.2 Km/sec, so spacecrafts do not have to change different orbits and spacecrafts are directly inserted into space. 
Mangalyaan had to undergo Orbital Maneuvers as it was launched from PSLV rocket. If it was to launch from GSLV MK III, Mangalyaan would take less time to reach Mars than it took with PSLV.
In Apogee and Perigee the orbit is of elliptical shape. When spacecraft travels from Apogee to Perigee it gains velocity die to gravity of Earth. Orbit of spacecraft becomes more elliptical. After completion of one round, again when spacecraft travels from Apogee to Perigee it gains more velocity than earlier giving more elliptical orbit. This transition is called Orbital Maneuver, where the orbits are changed. 
These Orbital Maneuvering is done till escape velocity is achieved and spacecraft leaves Earth's gravity.
When spacecraft enters in Mars' gravity, it has to be slowed down, otherwise it will fly-by across Mars and leave the desired trajectory. For slowing down the spacecraft, engine thrusters are used and spacecraft is settled in desired orbit.

Comments

Post a Comment

Popular posts from this blog

Shorte.st Review - Convert your Links to Money

-
Image
Shorte.st is a link shortner service which allows users to shorten links as well as earn money by sharing your short links. As compared to Adfly, LinkShrink and other Link Shorter Shorte.st is more trustworthy with good features and proper payments.  Shorte.st Review - How Shorte.st is better than other services? Shorte.st monetizes 5 views per IP in 24 hours. But I don't think it affects your earnings as nobody visits same link again and again within 24 hours. While many other link shortner services does not monetize first 3 views from every IP address. This affects you income to great extent.  How to use Shorte.st? Almost anyone can use Shorte.st, specially the bloggers. Small bloggers cannot earn enough money from there websites, due to low traffic and approval rejection by Ad Networks which are traffic hungry. Shorte.st is best option for small bloggers. They can monetize each and every link on their website and also use website scripts of shorte.st to ...
Read more

Samir Palnitkar Solution Manual Free Download PDF of Verilog HDL

-
Image
This is a solution guide to the exercises of the book "The Solution Manual of the Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar". Following are the Solutions to  Solution Manual on Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar , exercises of all chapters in the book.    Chapter 1  ----------------- No Exercises ----------------  Chapter 2 :  Hierarchical Modeling Concepts  Chapter 3 :  Basic Concepts  Chapter 4 :  Modules and Ports  Chapter 5:  Gate-level Modeling  Chapter 6 :  Dataflow Modeling  Chapter 7 : Behavioral Modeling  Chapter 8 :  Tasks and Functions Download Solution Manual:  Click on this link (Mega.nz Link) [Solution Manual to Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar] Preview of Solution Manual: For Verilog Programs: Go to Index of  Verilog Programming Tags: Verilog HDL solutio...
Read more

VLSI: 8-3 Encoder Dataflow Modelling with Testbench

-
Image
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3(     input d0,     input d1,     input d2,     input d3,     input d4,     input d5,     input d6,     input d7,     output q0,     output q1,     output q2     ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin                         ...
Read more

VLSI: 4-1 MUX Dataflow Modelling with Testbench

-
Image
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin                              // Initialize Inputs                              a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;        ...
Read more

Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench

-
Image
Verilog Code for Full Subtractor Structural/Gate Level Modelling module  full_sub(borrow,diff,a,b,c); output  borrow,diff; input  a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial  begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of  Verilog Programming
Read more