Latest Post
Space Facts: Part 7 - Mysterious Sun, Multiverse, Dark Matter
- Get link
- X
- Other Apps
Mysterious Sun:
Even though we know Sun from centuries, there are many mysteries of Sun remained unsolved. Most popular mystery is regarding Corona of Sun. Corona is outer layer of Sun's atmosphere. Corona is hotter than the inner layer Chromosphere.
Sun's visible surface Photosphere has temperature 5800°C. Outer layer of Photosphere is Chromosphere. Temperature of Chromosphere is estimated to be 4000°C. But astonishing fact is that Corona (outermost layer of Sun) is 3 million ℃. This is not possible if Heat Transfer laws are to be considered. To study about Sun in detail NASA sent a probe in 2018, ISRO will send Aaditya L1 probe to Langlargian L1 point from where Aaditya L1 will study the properties of Sun.
Are there Multiple Universes?
Multiverse theory is Hypothetical theory giving arguments of multiple universe are present in space-time. Many different Multiverse theory are formed. According to one, different universe may have different laws of Physics. As it could happen that in different universes the properties of subatomic particles may be different.
The Dark Matter Mystery:
Today we do not know what exactly is Dark Matter made up of, but we know it's presence and it's effects.
Some scientists believe that dark matter is made up of Neutrinos. Let's take an example proving presence of Dark Matter.
Andromeda is our neighbouring galaxy. Outer solar system of Andromeda are revolving around it's black hole at speed higher than expected.
To understand this case scientists calculated the total force acting on outer solar systems. This force is gravity of inner solar system and black hole. Surprisingly the force calculated was not enough to move outer solar system with speed in which they are revolving around. This extra force acting was from dark matter.
Dark matter has mass but it is not luminous, so we are not able to observe it even through powerful telescopes and observatories. What dark matter is formed of is not known, but we are sure it possess gravity.
- Get link
- X
- Other Apps
Popular posts from this blog
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
Verilog: 4 Bit Counter Behavioral Modelling using If Else Statement
Verilog Code for 4 Bit Counter Behavioral Modelling using If Else Statement module 4_bit_Count( input clock, reset, output [3:0]dout ); reg [3:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else dout <= dout + 1; end endmodule Xillinx Output: 4 Bit Counter Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: 4 to 1 Multiplexer Behavioral Modelling with Testbench Code
Verilog Code 4-1 Multiplexer Behavioral Modelling using Case Statement module Mux_4to1 ( input [3:0] i, input s1, s0, output out ); always @(i or s1 or s0) case({s1, s0}) 0 : out = i[0]; 1 : out = i[1]; 2 : out = i[2]; 3 : out = i[3]; default : out = 1’bx; endcase endmodule // test-bench initial begin i=1'b1010; s1=0; s0=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 s1 = 0; s0= 1; #100 s1 = 1; s0= 0; #100 s1 = 1; s0= 1; end
VLSI: 3-8 Decoder Dataflow Modelling with Testbench
Verilog Code for 3-8 Decoder Dataflow Modelling module decoder3_to_8( input x, input y, input z, output d0, output d1, output d2, output d3, output d4, output d5, output d6, output d7 ); assign d0 = xn & yn & zn; assign d1 = xn & yn & z; assign d2 = xn & y & zn; assign d3 = xn & y & z; assign d4 = x & yn & z; assign d5 = x & yn & z; assign d6 = x & y & zn; assign d7 = x & y & z; assign xn = ~ x; assign yn = ~ y; assign zn = ~ z; endmodule //Testbench code for 3-8 Decoder Dataflow Modelling ...
Comments
Post a Comment