Latest Post

Space Facts: Part 8 - Birth of Universe, Cosmic Inflation

-
The Birth of Universe:
It is believed that before Big bang universe was a tiny point having infinite density and infinite temperature. Surrounding of that point was void, having no matter, no temperature and no time.
After Big-Bang (a great explosion from that singular point) the 'matter' spread in all directions at the speed of light. According to theory of relativity, if an object travels at a speed of light, time dimension for that object becomes zero. In other words time stops for that object. So within no time that minute zero dimensional point became an expanding universe. This expansion of Universe after Big-Bang is called Cosmic Inflation.

Now what is Cosmic Inflation Theory?

Cosmos means Universe and Inflation refers to Spread of Universe. Big-Bang theory does not explain from where that point universe came into existence and what happened after Big-Bang. Cosmic Inflation Theory explains what happened after Big-Bang.
Cosmic Inflation Theory starts when the speed of inflation decreased than speed of light. That's the reason why Big-Bang theory is explained in 3 dimensions but Cosmic Inflation Theory is explained in 4 dimensions. The 4th dimension is Time. Time started when universe was spreading with speed lower than the speed of light.

What Einstein thought on Cosmic Inflation?

Einstein compared the universe with balloon. Balloon inflates till we blow air in it and shrinks after reaching a saturation point. Using this assumption he gave his "Special Theory of Relativity".
But today most of the Astrophysicists believe that universe will not shrink and will keep on expanding. Recent discoveries also put light on theory, that universe is still expanding but an uneven expansion of Universe is taking place.
Although Einstein made some mistakes in his assumptions most of the equations given by his theory of relativity has proved to be true!!

Comments

Post a Comment

Popular posts from this blog

VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench

-
Image
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs ...
Read more

VLSI: 4-1 MUX Dataflow Modelling with Testbench

-
Image
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin                              // Initialize Inputs                              a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;        ...
Read more

Verilog: 4 Bit Counter Behavioral Modelling using If Else Statement

-
Image
Verilog Code for 4 Bit Counter Behavioral Modelling using If Else Statement module 4_bit_Count(      input clock, reset,      output [3:0]dout     ); reg [3:0]dout;  initial dout = 0;   always @ (posedge (clock))    begin            if (reset)                 dout <= 0;            else                dout <= dout + 1;     end endmodule Xillinx Output: 4 Bit Counter Behavioral Modelling Response   Also See: List of Verilog Programs
Read more

Verilog: 4 to 1 Multiplexer Behavioral Modelling with Testbench Code

-
Verilog Code 4-1 Multiplexer Behavioral Modelling using Case Statement module Mux_4to1 ( input [3:0] i, input s1, s0, output out ); always @(i or s1 or s0) case({s1, s0}) 0 : out = i[0]; 1 : out = i[1]; 2 : out = i[2]; 3 : out = i[3]; default : out = 1’bx; endcase endmodule // test-bench initial begin i=1'b1010; s1=0; s0=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 s1 = 0; s0= 1; #100 s1 = 1; s0= 0; #100 s1 = 1; s0= 1; end
Read more

VLSI: 3-8 Decoder Dataflow Modelling with Testbench

-
Image
Verilog Code for 3-8 Decoder Dataflow Modelling module decoder3_to_8(     input x,     input y,     input z,     output d0,     output d1,     output d2,     output d3,     output d4,     output d5,     output d6,     output d7     ); assign d0 = xn & yn & zn; assign d1 = xn & yn & z; assign d2 = xn & y & zn; assign d3 = xn & y & z; assign d4 = x & yn & z; assign d5 = x & yn & z; assign d6 = x & y & zn; assign d7 = x & y & z; assign xn = ~ x; assign yn = ~ y; assign zn = ~ z; endmodule //Testbench code for 3-8 Decoder Dataflow Modelling ...
Read more