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VLSI: 4-1 Multiplexer (MUX) Dataflow Modelling

-
module Four_to_One_MUX(
    input s0,
    input s1,
    input i0,
    input i1,
    input i2,
    input i3,
    output out
    );
assign y0 = (i0 & (~s0) & (~s1));
assign y1 = (i1 & (~s0) & s1);
assign y2 = (i2 & s0 & (~s1));
assign y3 = (i3 & s0 & s1);
assign out = (y0 | y1 | y2 | y3);

 endmodule

MUX using Conditional Statement:


module Four_to_One_MUX(
    input s0,
    input s1,
    input i0,
    input i1,
    input i2,
    input i3,
    output out
    );
assign out = s0 ? (s1 ? i3 : i2) : (s1 ? i1 : i0);


endmodule



             

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