VLSI: Half Subtractor - Full Subtractor Dataflow Modelling
Half Subtractor:
Verilog Module Code:
module half_subtractor(
input a,
input b,
output diff
output borr);
output borr);
assign diff = a ^ b ;
assign borr = ( (~ a) & b ) ;
assign borr = ( (~ a) & b ) ;
endmodule
Full Subtractor:
Verilog Module Code:
module full_subtractor(
input a,
input b,
input bin,
input bin,
output diff
output borr);
assign x = a ^ b ;
assign y = (~x) & bin ;
assign z = (~a) & b ;
output borr);
assign x = a ^ b ;
assign y = (~x) & bin ;
assign z = (~a) & b ;
assign diff = x ^ bin ;
assign borr = y | z ;
assign borr = y | z ;
endmodule
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