VLSI: Half Adder-Full Adder Dataflow Modelling
Half Adder:
Verilog Module Code:
module half_adder(
input a,
input b,
output sum
output carry);
output carry);
assign sum = a ^ b ;
assign carry = a & b;
assign carry = a & b;
endmodule
Full Adder:
Verilog Module Code:
module full_adder(
input a,
input b,
input cin,
input cin,
output sum
output carry);
assign x = a ^ b ;
assign y = x & cin ;
assign z = a & b ;
output carry);
assign x = a ^ b ;
assign y = x & cin ;
assign z = a & b ;
assign sum = x ^ cin ;
assign carry = y | z ;
assign carry = y | z ;
endmodule
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