Latest Post

VLSI: Encoder Gate Level Modelling

- 
module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
 input d0,d1,d2,d3,d4,d5,d6,d7;
 output a,b,c;
 or (a,d4,d5,d6,d7);
 or (b,d2,d3,d6,d7);
 or (c,d1,d3,d5,d7);
endmodule

Popular posts from this blog

Samir Palnitkar Solution Manual Free Download PDF of Verilog HDL

-
Image
This is a solution guide to the exercises of the book "The Solution Manual of the Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar". Following are the Solutions to  Solution Manual on Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar , exercises of all chapters in the book.    Chapter 1  ----------------- No Exercises ----------------  Chapter 2 :  Hierarchical Modeling Concepts  Chapter 3 :  Basic Concepts  Chapter 4 :  Modules and Ports  Chapter 5:  Gate-level Modeling  Chapter 6 :  Dataflow Modeling  Chapter 7 : Behavioral Modeling  Chapter 8 :  Tasks and Functions Download Solution Manual:  Click on this link (Mega.nz Link) [Solution Manual to Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar] Preview of Solution Manual: For Verilog Programs: Go to Index of  Verilog Programming Tags: Verilog HDL solutio...
Read more

VLSI: 8-3 Encoder Dataflow Modelling with Testbench

-
Image
Verilog Code for 8-3 Encoder Dataflow Modelling module encoder_8_to_3(     input d0,     input d1,     input d2,     input d3,     input d4,     input d5,     input d6,     input d7,     output q0,     output q1,     output q2     ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule //Testbench code for 8-3 Encoder Dataflow Modelling initial begin                         ...
Read more

VLSI: 4-1 MUX Dataflow Modelling with Testbench

-
Image
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin                              // Initialize Inputs                              a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0;        ...
Read more

Verilog: 4 - 2 Encoder Structural/Gate Level Modelling with Testbench

-
Image
Verilog Code for 4-2 Encoder Structural/Gate Level Modelling module  encode_4_to_2(      input  d0,d1,d2,d3,      output  a0,a1     ); wire  x,y,z; not  g1(x,d2); and  g2(y,x,d1); or  g3(a0,y,d3); or  g4(a1,d2,d3); endmodule //Testbench code for 4-2 Encoder Structural/Gate Level Modelling initial  begin // Initialize Inputs  d0 = 1;d1 = 0;d2 = 0;d3 = 0; // Wait 100 ns for global reset to finish  #100; // Add stimulus here  #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;  #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;  #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1; end Output: Verilog 4-2 Encoder Response Other Verilog Programs: Go to Index of  Verilog Programming
Read more

Verilog: 4 Bit Full Adder Behavioral Modelling with Testbench Code

-
Image
Verilog Code for 4 Bit Full Adder Behavioral Modelling with Testbench Code module 4_bit_Add(      input [3:0]a,b,     input cin,      output [3:0]sum,     output cout     ); reg [3:0]sum;  reg cout;   always @ (a or b or cin)    assign {cout,sum}= a + b + cin; endmodule //Testbench code for 4 Bit Full Adder Behavioral Modelling initial  begin // Initialize Inputs   a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100 a=4; b=9; cin=1;  #100 a=15; b=5; cin=1;  #100 a=7; b=5; cin=0;  #100 a=6; b=10; cin=1;  end initial begin  #100   $monitor (“ a = %b, b = %b, cin = %b, sum = %b, cout = %b”, a, b, cin, sum, cout);  end  endmodule Xillinx Output: 4 Bit Full Adder Behavioral Modelling Response Also See: List of Verilog Programs
Read more