VLSI: Half Adder and Full Adder Gate Level Modelling
Half Adder:
module HalfAdder(
input A,
input B,
output sum,
output carry
);
xor (sum,A,B);
and (carry,A,B);
endmodule
Full Adder:
module FullAdder(
input A,
input B,
input Cin,
output sum,
output carry
);
wire a1, a2, a3;
xor g1(a1,A,B);
and g4(a2,A,B);
and g3(a3,a1,Cin);
or g5(carry,a2,a3);
xor g2(sum,a1,Cin);
endmodule
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