VLSI: Logic Gates Dataflow Modelling
AND Gate:
Verilog Module Code:
module and_gate(
input a,
input b,
output c );
assign c = a & b;
endmodule
OR Gate:
Verilog Module Code:
module or_gate(
input a,
input b,
output c );
assign c = a | b;
endmodule
NAND Gate:
Verilog Module Code:
module nand_gate(
input a,
input b,
output c );
assign c = ~ ( a & b );
endmodule
NOR Gate:
Verilog Module Code:
module nor_gate(
input a,
input b,
output c );
assign c = ~ ( a | b );
endmodule
XOR Gate:
Verilog Module Code:
module xor_gate(
input a,
input b,
output c );
assign c = a ^ b ;
endmodule
XNOR Gate:
Verilog Module Code:
module xnor_gate(
input a,
input b,
output c );
assign c = ~ ( a ^ b ) ;
endmodule
NOT Gate:
Verilog Module Code:
module not_gate(
input a,
output c );
assign c = ~ a ;
endmodule
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