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Verilog: 8 to 1 MUX Behavioral Modelling using Verilog Case Statement with Testbench Code

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Verilog Code for 8 to 1 MUX Behavioral Modelling using Verilog Case Statement with Testbench Code

module 8_1_MUX(
    input [7:0]i,
    input s2,s1,s0,
    output out  
    );
reg out; 
always @ (i or s2 or s1 or s0) 
case ({s2,s1,s0})
    0 : out = I[0]; 
    1 : out = I[1]; 
    2 : out = I[2]; 
    3 : out = I[3]; 
    4 : out = I[4]; 
    5 : out = I[5]; 
    6 : out = I[6]; 
    7 : out = I[7]; 
    default : out = 1’bx;
endcase 
endmodule
//Testbench code for 8 to 1 MUX (Multiplexer) Behavioral Modelling using Verilog Case Statement
initial begin
// Initialize Inputs 
i=8’b 10101010; s2=0; s1=0; s0=0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s2=0; s1=0; s0=1; 
#100; s2=0; s1=1; s0=0; 
#100; s2=0; s1=1; s0=1;
#100; s2=1; s1=0; s0=0; 
#100; s2=1; s1=0; s0=1; 
#100; s2=1; s1=1; s0=0; 
#100; s2=1; s1=1; s0=1; 
end
initial begin 
#100 
$monitor(“I=%b, s2=%b, s1=%b, s0=%b, out=%b”, I, s2, s1,
 s0, out); 
end 
endmodule

Xillinx Output:
8 to 1 Multiplexer Verilog Code using Case Statement Behavioral Modelling
8 - 1 MUX Behavioral Modelling Response

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