Verilog: 1-2 De-Multiplexer (DEMUX) using Case Statement Behavioral Modelling with Testbench Code
Verilog Code for 1 to 2 DEMUX Behavioral Modelling using Case Statement with Testbench Code
module 1_2_DEMUX(
input i0,
input s0,
output out1,
output out2
);
always @ (i0 or s0)case (s0)0: out1 = i0;1: out2 = i0;default: out1 = 1'bx;out2 = 1'bx;endcase
endmodule//Testbench code for 1 to 2 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement
initial begin// Initialize Inputsi0 = 1;s0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s0 = 1;
#100; s0 = 0;end
Output:
 |
| 1-2 DeMUX Response |
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