Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code

module 1_4_DEMUX(
    input i,
    input s1, s0, 
    output [3:0]out  
    );
reg [3:0]out; 
always @ (i or s0 or s1) 
case ({s1,s0})
    0: out0 = i;
    1: out1 = i;
    2: out2 = i;
    3: out3 = i;
    default: out = 4'bxxxx;
endcase 
endmodule
//Testbench code for 1 to 4 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
i = 1;s1 = 0;s0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; s1=0; s0=1; 
#100; s1=1; s0=0;

#100; s1=1; s0=1;  
end
initial begin 
#100;
$monitor(“I=%b, s1=%b, s0=%b, out=%b”, I, s1,
 s0, out);
end
endmodule