Verilog: 2-1 Multiplexer with Case Statement Behavioral Modelling with Testbench Code
Verilog Code for 2 to 1 MUX Behavioral Modelling using Case Statement with Testbench Code
module 2_1_MUX(
input i0,
input i1,
input s0,
output out
);
always @ (i0 or i1 or s0)case (s0)0: out = i0;1: out = i1;default: out = 1'bx;endcase
endmodule//Testbench code for 2 to 1 MUX (Multiplexer)Behavioral Modelling using Case Statement
initial begin// Initialize Inputsi0 = 1;i1 = 1;s0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s0 = 0;
#100; s0 = 1;end
Output:
 |
| 2 - 1 MUX Behavioral Modelling Response |
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