Verilog: 3 to 8 Decoder Behavioral Modelling using Case Statement with Testbench Code

Verilog Code for 3 to 8 Decoder Behavioral Modelling using Case Statement with Testbench Code

module 3_8_DEC(
    input [3:0]din,
    output [7:0]dout  
    );
reg [7:0]dout; 
always @ (din) 
case (din)
    0 : dout[0] = 1; 
    1 : dout[1] = 1; 
    2 : dout[2] = 1; 
    3 : dout[3] = 1; 
    4 : dout[4] = 1; 
    5 : dout[5] = 1; 
    6 : dout[6] = 1; 
    7 : dout[7] = 1; 
    default : dout = 8’bxxxxxxxx;
endcase 
endmodule
//Testbench code for 3 to 8 Decoder Behavioral Modelling using Case Statement
initial begin
// Initialize Inputs 
din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; din=0; 
#100; din=1; 
#100; din=2; 
#100; din=3;
#100; din=4; 
#100; din=5; 
#100; din=6; 
#100; din=7;  
end
initial begin 
#100 
$monitor(“din=%b, dout=%b”, din, dout); 
end 
endmodule 

Xillinx Output:

3 - 8 Decoder Behavioral Modelling Response