Verilog: Half Subtractor Behavioral Modelling with Testbench Code
Verilog Code Half Subtractor Behavioral Modelling
module Half_Sub (
input a, b;
output diff, borr );
always @(a or b)
assign {borr,diff} = (~a) + b;
endmodule
// test-bench
initial begin
a=0; b=0;
#100;
//wait 100ns for global reset to finish
//add stimulus here
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
initial begin
#100 $monitor(“a=%b, b=%b, diff=%b, borr=%b”, a, b, diff, borr);
end
endmodule
Xilinx Output:
Half Subtractor Behavioral Modelling Verilog Code
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