Verilog: Half Adder Behavioral Modelling with Testbench Code
Verilog Code Half Adder Behavioral Modelling
module Half_Adder (
input a, b;
output sum, carry );
always @(a or b)
assign {carry,sum} = a + b;
endmodule
// test-bench
initial begin
a=0; b=0;
#100;
//wait 100ns for global reset to finish
//add stimulus here
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
initial begin
#100 $monitor(“a=%b, b=%b, sum=%b, carry=%b”, a, b, sum, carry);
end
endmodule
Xilinx Output:
 |
| Half Adder Verilog Code Behavioral Modelling |
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