Full Subtractor Verilog Code in Behavioral Modelling with Testbench Code
Full Subtractor Verilog Code in Behavioral Modelling
Xilinx Output:
module Full_Sub (
input a, b, bin;
output diff, borr );
always @(a or b or bin)
assign {borr,diff} = (~a) + b + bin;
endmodule
// test-bench
initial begin
a=0; b=0; bin=0;
#100;
//wait 100ns for global reset to finish
//add stimulus here
#100 a=0; b=1; bin=0;
#100 a=1; b=0; bin=0;
#100 a=1; b=1; bin=0;
end
initial begin
#100 $monitor(“a=%b, b=%b, bin=%b, diff=%b, borr=%b”, a, b, bin, diff, borr);
end
endmodule
Xilinx Output:
 |
| Full Subtractor Verilog Code Behavioral Modelling |
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