Verilog: NOT Gate Behavioral Modelling with Testbench Code
Verilog Code NOT Gate Behavioral Modelling
// main
module NOT_GATE (
input a;
output out );
reg out;
always @(a)
begin
if(a==0)
out = 1’b1;
else
out = 1’b0;
endmodule
// test-bench
initial begin
a=0;
#100;
//wait 100ns for global reset to finish
//add stimulus here
#100 a=0;
#100 a=1;
end
initial begin
#100 $monitor(“a=%b, out=%b”, a, out);
end
endmodule
Xilinx Output:
 |
| Not Gate Behavioral Modelling |
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