Verilog: XOR Gate Behavioral Modelling with Testbench Code

Verilog Code XOR Gate Behavioral Modelling

module XOR_GATE ( 
input a, b, 
output out ); 
reg out; 
always @(a or b) 
begin
if(a==b) 
out = 1’b0; 
else
out = 1’b1; 
endmodule

//test-bench 
initial begin 

a=0; b=0; 
#100; //wait 100ns for global reset to finish 
//add stimulus here 
#100 a=0; b=1; 
#100 a=1; b=0; 
#100 a=1; b=1; 
end

initial begin 
#100 $monitor(“a=%b, b=%b, out=%b”, a, b, out); 
end
endmodule

Xilinx Output:

XOR Gate Verilog Behavioral Modelling