Verilog: VLSI Code for D Flip Flop with Testbench Dataflow Modelling

Verilog Code for D Flip Flop Dataflow Modelling

module DFF(
input d,
input en,
output q,
output qb
);
 
assign a = ( en & ( ~ d ));
assign b = ( en & d );
assign q = ~ ( a | qb );
assign qb = ~ ( b | q );

endmodule
 
//Testbench 

initial begin
// Initialize Inputs
d = 0;
en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100;d = 0;en = 1;
#100;d = 1;en = 0;
#100;d = 1;en = 1;
 
end 

Xillinx Output:

D Flip Flop Dataflow Modelling

 

 

Also See:List of Verilog Programs