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Verilog: 1 Bit Magnutude Comparator Dataflow Modelling with Testbench Code

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 Verilog Code for 1 Bit Magnitude Comparator Dataflow Modelling 

module comparator_1_bit(
input x,
input y,
output a, //x>y
output b, //x=y
output c //x<y
);
assign xn = ~ x;
assign yn = ~ y;
assign a = x & yn;
assign c = xn & y;
assign b = ~ ( a | c ); 

endmodule
 
//Testbench 

initial begin
// Initialize Inputs
x = 0;y = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here 
#100; x=0;y=1;
#100; x=1;y=0;
#100; x=1;y=1;
 
end

Xillinx Output:


1 Bit Magnitude Comparator Dataflow Modelling

 
 
Also See:List of Verilog Programs

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