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Verilog: 1 to 2 DeMultiplexer (1-2 DEMUX) Dataflow Modelling with Testbench Code

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 Verilog Code for 1 to 2  DeMultiplexer Dataflow Modelling 

module DEMUX_1_to_2(
input s,
input d,
output y0,
output y1
);

assign sn = ~ s;
assign y0 = sn & d;
assign y1 = s & d;

endmodule
 
//Testbench 

initial begin
// Initialize Inputs
s = 0;
d = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; s=0;d=1;
#100; s=1;d=0;
#100; s=1;d=1; 
 
end

Xillinx Output:



1-2 DEMUX Verilog Coding
1-2 DEMUX Verilog Coding

 
 
Also See:

List of Verilog Programs

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