Stellar Coding - Verilog, Filter Design and more..

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1. Interval Halving Method Algorithm in C #include<stdio.h> double myFun(double x); int main() {  double a, b, y, x, xm, x1, x2, fx1, fx2, fxm, L, t=0.01;  printf("Enter a:");  scanf("%lf",&a);   //Upper Bound  printf("Enter b:");  scanf("%lf",&b);    //Lower Bound  xm = (a + b)/2;  jump:  L = b-a;  x1 = a + (L/4);  x2 = b - (L/4);  printf("\n\na = %.2lf",a);  printf("\nb = %.2lf",b);  printf("\nx1 = %.2lf",x1);  printf("\nx2 = %.2lf",x2);  printf("\nxm = %.2lf",xm);  printf("\nL = %.2lf",L);  fx1 = myFun(x1);  printf("\nf(x1) = %.2lf",fx1);  fx2 = myFun(x2);  printf("\nf(x2) = %.2lf",fx2);  fxm = myFun(xm);  printf("\nf(xm) = %.2lf",fxm);  if(L > t)  {   if (fx1 < fxm)   {    a = a;    b = xm;    xm = x1;    got...

#include<stdio.h> #include<conio.h> void main() { int a=12; float b=24.25; char c='a'; clrscr(); printf("\n Address of A : %u",&a); printf("\n Address of B : %u",&b); printf("\n Address of C : %u",&c); getch(); } Output: Address of A : 65524 Address of B : 65520 Address of C : 65519 C Programs: ------------------------ |   Basic Programs    |   Loop Programs    |   Conditional Programs    |   Matrix Programs    |   Array Programs    |   String Programs    |   File Handling    |   Other Programs    |   Graphics in C     |  Pattern Programs ------------------------

4 Pole Bandpass Active Filter Input Output Filter Type Butterworth Chebyshev 0.1 dB Bessel Capacitors (uF) Center Freq (Hz) 3dB Bandwidth (Hz) Voltage Gain C1,C2,C3,C4 (uF) R1 (K Ohms) R2 (K Ohms) R3 (K Ohms) R4 (K Ohms) R5 (K Ohms) R6 (K Ohms) Section 1 2 Q Freq Active Lowpass Calculator: 1. 2 Pole Active Lowpass with Unity Gain 2. 2 Pole Active Lowpass with Gain 3. 3 Pole Active Lowpass Filter Active Highpass Calculator: 1. 2 Pole Active Highpass with Unity Gain 2. 2 Pole Active Highpass with Gain 3. 3 Pole Active Highpass Filter Active Bandpass Calculator: 1. 2 Pole Active BandPass Filter 2. 4 Pole Active BandPass Filter 3. 6 Pole Active BandPass Filter

Filter Designer Filter Designer tool can be used for designing Active Lowpass, Active Highpass and Active Bandpass Filters. Calculate the values of capacitors, resistors, Q values and frequencies of active filter. Note: Filter Designer Tool works best on Computers, we are currently optimizing this tool to work on smartphones. -------------------------------------------------------- Active Lowpass Calculator: 1. 2 Pole Active Lowpass with Unity Gain 2. 2 Pole Active Lowpass with Gain 3. 3 Pole Active Lowpass Filter Active Highpass Calculator: 1. 2 Pole Active Highpass with Unity Gain 2. 2 Pole Active Highpass with Gain 3. 3 Pole Active Highpass Filter Active Bandpass Calculator: 1. 2 Pole Active BandPass Filter 2. 4 Pole Active BandPass Filter 3. 6 Pole Active BandPass Filter Notch Filter Calculator: 1. 2 Op-Amp Notch Filter Calculator Sallen Key Filter Calculator: 1. Sallen Key Lowpass Butterworth Filter Calculator

Verilog Code for 8 to 3 Encoder Dataflow Modelling module encoder_8_to_3( input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, output q0, output q1, output q2 ); assign q0 = ( d1 | d3 | d5 | d7 ); assign q1 = ( d2 | d3 | d6 | d7 ); assign q2 = ( d4 | d6 | d5 | d7 ); endmodule   //Testbench initial begin // Initialize Inputs d0 = 1; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 1;d6 = 0;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 1;d7 = 0; #100;d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 1;    end Xillinx Output: 8 to 3 Encoder Xilinx Output   ...

  Verilog Code for 1 to 8 DeMultiplexer Dataflow Modelling module demux_1_to_8( input d, input s0, input s1, input s2, output y0, output y1, output y2, output y3, output y4, output y5, output y6, output y7 ); assign s0n = ~ s0; assign s1n = ~ s1; assign s2n = ~ s2;  assign y0 = d & s0n & s1n & s2n; assign y1 = d & s0 & s1n & s2n; assign y2 = d & s0n & s1 & s2n; assign y3 = d & s0 & s1 & s2n; assign y4 = d & s0n & s1n & s2; assign y5 = d & s0 & s1n & s2; assign y6 = d & s0n & s1 & s2; assign y7 = d & s0 & s1 & s2;   endmodule //Testbench code for 1-8 DEMUX Dataflow Modelling initial begin // Initialize Inputs d = 0;s0 = 0;s1 = 0;s2 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; d = 1;s0 = 0;s1 = 0;s2 = 0; #100; d = 1;s0 = 1;s1 = 0;s2 = 0; #100; d = 1;s0 = 0;s1 = 1;s2 = 0; #100; d = 1;s0 = 1;s1 = 1;s2 = 0; #100; d = 1;s0 = 0;s1 = 0;s2 = 1; ...