Verilog: Full Adder Behavioral Modelling with Testbench Code

 Verilog Code Full Adder Behavioral Modelling

module Full_Adder ( 
input a, b, cin; 
output sum, carry ); 
always @(a or b or cin) 
assign {carry,sum} = a + b + cin; 
endmodule

// test-bench 
initial begin 
a=0; b=0;
 #100; 
//wait 100ns for global reset to finish 
//add stimulus here 
#100 a=0; b=1; cin=1; 
#100 a=1; b=0; cin=1; 
#100 a=1; b=1; cin=1; 
end
initial begin 
#100 $monitor(“a=%b, b=%b, cin=%b, sum=%b, carry=%b”, a, b, cin, sum, carry); 
end
endmodule

Xilinx Output:

Verilog code for Full Adder Behavioral Modelling