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VLSI: AND Gate Dataflow Modelling with Testbench
Verilog Code for AND gate Dataflow Modelling module ANDgate( input a, input b, output c ); assign c = a & b; endmodule //Testbench code for AND gate Dataflow Modelling initial begin // Initialize Inputs a = 0;b = 0; // Wait 100 ns for global reset to finish #100 a = 0; b = 1; #100 a = 1; b = 0; #100 a = 1; b = 1; e nd Output:
VLSI: 1 Bit Magnitude Comparator Dataflow Modelling with Testbench
Verilog Code for 1 Bit Magnitude Comparator Dataflow Modelling module comparator_1_bit( input x, input y, output a, //x>y output b, //x=y output c //x<y ); assign xn = ~ x; assign yn = ~ y; assign a = x & yn; assign c = xn & y; assign b = ~ ( a | c ); endmodule //Testbench code for 1 Bit Magnitude Comparator Dataflow Modelling initial begin // Initialize Inputs ...
Barcode Generator Tool Free
Free Generate Barcode using Javascript and HTML: Barcode Generator tool is an innovative tool to generate different types of barcodes. This tool made using Javascript, CSS and HTML. An ultimate tool to generate different type of barcodes. An interesting aspect of using this tool is that this tool can work even in offline mode. As javascript and css files are integrated inside HTML itself. You can generate different types of barcodes. Change the foreground and background colors, change the font style, change the font color, vary the size to barcode, size of font, etc. An interesting tool for javascript enthusiastic. Download the source code from the below given button and start exploring different types of barcodes !! Watch Youtube Tutorial Video: Watch the Youtube video to see how the settings work, and feel free to modify the code. This is just the beta version, tasks to do: Implement a javascript to save the barcode on your computer. Barcode is generated in "svg" format. ...
Optimization: Interval Halving Method
1. Interval Halving Method Algorithm in C #include<stdio.h> double myFun(double x); int main() { double a, b, y, x, xm, x1, x2, fx1, fx2, fxm, L, t=0.01; printf("Enter a:"); scanf("%lf",&a); //Upper Bound printf("Enter b:"); scanf("%lf",&b); //Lower Bound xm = (a + b)/2; jump: L = b-a; x1 = a + (L/4); x2 = b - (L/4); printf("\n\na = %.2lf",a); printf("\nb = %.2lf",b); printf("\nx1 = %.2lf",x1); printf("\nx2 = %.2lf",x2); printf("\nxm = %.2lf",xm); printf("\nL = %.2lf",L); fx1 = myFun(x1); printf("\nf(x1) = %.2lf",fx1); fx2 = myFun(x2); printf("\nf(x2) = %.2lf",fx2); fxm = myFun(xm); printf("\nf(xm) = %.2lf",fxm); if(L > t) { if (fx1 < fxm) { a = a; b = xm; xm = x1; got...
C Program: Show Address of Variable using Pointers
#include<stdio.h> #include<conio.h> void main() { int a=12; float b=24.25; char c='a'; clrscr(); printf("\n Address of A : %u",&a); printf("\n Address of B : %u",&b); printf("\n Address of C : %u",&c); getch(); } Output: Address of A : 65524 Address of B : 65520 Address of C : 65519 C Programs: ------------------------ | Basic Programs | Loop Programs | Conditional Programs | Matrix Programs | Array Programs | String Programs | File Handling | Other Programs | Graphics in C | Pattern Programs ------------------------
4 Pole Bandpass Active Filter Calculator
4 Pole Bandpass Active Filter Input Output Filter Type Butterworth Chebyshev 0.1 dB Bessel Capacitors (uF) Center Freq (Hz) 3dB Bandwidth (Hz) Voltage Gain C1,C2,C3,C4 (uF) R1 (K Ohms) R2 (K Ohms) R3 (K Ohms) R4 (K Ohms) R5 (K Ohms) R6 (K Ohms) Section 1 2 Q Freq Active Lowpass Calculator: 1. 2 Pole Active Lowpass with Unity Gain 2. 2 Pole Active Lowpass with Gain 3. 3 Pole Active Lowpass Filter Active Highpass Calculator: 1. 2 Pole Active Highpass with Unity Gain 2. 2 Pole Active Highpass with Gain 3. 3 Pole Active Highpass Filter Active Bandpass Calculator: 1. 2 Pole Active BandPass Filter 2. 4 Pole Active BandPass Filter 3. 6 Pole Active BandPass Filter
Filter Designer
Filter Designer Filter Designer tool can be used for designing Active Lowpass, Active Highpass and Active Bandpass Filters. Calculate the values of capacitors, resistors, Q values and frequencies of active filter. Note: Filter Designer Tool works best on Computers, we are currently optimizing this tool to work on smartphones. -------------------------------------------------------- Active Lowpass Calculator: 1. 2 Pole Active Lowpass with Unity Gain 2. 2 Pole Active Lowpass with Gain 3. 3 Pole Active Lowpass Filter Active Highpass Calculator: 1. 2 Pole Active Highpass with Unity Gain 2. 2 Pole Active Highpass with Gain 3. 3 Pole Active Highpass Filter Active Bandpass Calculator: 1. 2 Pole Active BandPass Filter 2. 4 Pole Active BandPass Filter 3. 6 Pole Active BandPass Filter Notch Filter Calculator: 1. 2 Op-Amp Notch Filter Calculator Sallen Key Filter Calculator: 1. Sallen Key Lowpass Butterworth Filter Calculator
Popular posts from this blog
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = ...