Verilog: VLSI Code for JK Flip Flop with Testbench Dataflow Modelling
Verilog Code for J K Flip Flop Dataflow Modelling
module JK_flipflop(
input j,
input k,
input en,
output q,
output qb
);assign a = ~ ( qb & j & en );
assign b = ~ ( q & k & en );
assign q = ~ ( a & qb );
assign qb = ~ ( b & q & (~ k) );
endmodule//Testbench
initial begin
// Initialize Inputs
j = 0;
k = 0;
en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here#100;j = 0;k = 0;en = 1;
#100;j = 0;k = 1;en = 1;
#100;j = 1;k = 0;en = 1;
#100;j = 1;k = 1;en = 1;
#100;j = 0;k = 1;en = 0;
#100;j = 1;k = 0;en = 0;
#100;j = 1;k = 1;en = 0;
#100;j = 0;k = 0;en = 1;#100;j = 0;k = 1;en = 1;
#100;j = 1;k = 0;en = 1;
#100;j = 1;k = 1;en = 1;end
Xillinx Output:
| JK Flip Flop Dataflow Modelling |
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