Verilog: 1 to 4 DeMultiplexer (1-4 DEMUX) Dataflow Modelling with Testbench Code
Verilog Code for 1 to 4 DeMultiplexer Dataflow Modelling
module demux_1_to_4(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);assign s1n = ~ s1;
endmodule
assign s0n = ~ s0;
assign y0 = d& s0n & s1n;
assign y1 = d & s0 & s1n;
assign y2 = d & s0n & s1;
assign y3 = d & s0 & s1;//Testbench code for 1-4 DEMUX Dataflow Modelling
initial begin // Initialize Inputs d = 1;
s0 = 0;
s1 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100;d = 1;s0 = 1;s1 = 0;
#100;d = 1;s0 = 0;s1 = 1;
#100;d = 1;s0 = 1;s1 = 1;end
Xillinx Output:
 |
| 1-4 DEUX Dataflow Modelling |
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