Latest Post
Inkarnate - Fantasy Map Maker
- Get link
- X
- Other Apps
Inkarnate Maps
Inkarnate is a fantasy map making online tool, used to make DnD (Dragons and Dungeons) maps, Battle maps, fantasy World maps for games and novels. Inkarnate is easy to use and with lots of features. Inkarnate has free as well as pro services. For professional map makers I would suggest to use its pro services which has 5$ for a month and 25$ for a year plans. Free services is majorly for hobbyists who want to try till cool map making tool. Although you can make attractive maps using free Inkarnate account, pro services fives you more assets, better resolution of maps (upto 4K), and many other features.
Below I have uploaded some fantasy maps made by me,
Village [Settlement Map]:
Gamora [Settlement Map]:
Map Making Tips for Inkarnate:
1. Jagged coastlines - If your coastline is just a straight line, it will look artificially made. Natural coastlines have curves and jagged edges and little islands or rocks next to them as a result of erosion by waves.
2. Rivers - A lot of people forget that rivers flow from higher elevation to lower elevation and that they meander as they become slower. Again, a straight line won't do (that's not a river, that's a canal) and never have river diverge into two separate rivers. Rivers don't do that - they converge into a bigger river.
3. Areas with different climates - If you want to have a desert or arctic area next to your grasslands/plains area, you need to separate it somehow. The easiest thing to is put in a mountain range which can act as a barrier between them.
4. Underwater Objects - You can create underwater objects by using opacity features of Inkarnate (only available in pro version).
Outpost 1 [Battlemap]:
Link to Inkarnate: https://inkarnate.com/
Inkarnate Tutorials:
Also See:
- Get link
- X
- Other Apps
Popular posts from this blog
VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Verilog: 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code
Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code module 4_2_ENC( input [3:0]din, output [1:0]dout ); reg [1:0]dout; always @ (din) case (din) 1 : dout[0] = 0; 2 : dout[1] = 1; 4 : dout[2] = 2; 8 : dout[3] = 3; default : dout = 2’bxx; endcase endmodule //Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement initial begin // Initialize Inputs din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; din=1; #100; din=2; #100; din=4; #100; din=8; end initial begin #100 $monitor (“ din=%b, dout=%b”, din, dout); end endmodule Xillinx Output: 4 - 2 Encoder Behavioral Modelling Verilog Response
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
Verilog: 2 - 4 Decoder Structural/Gate Level Modelling with Testbench
Verilog Code for 2-4 Decoder Structural/Gate Level Modelling 2-4 Line Decoder module decoder_2_to_4( input a0, input a1, output d0, output d1, output d2, output d3 ); not (an0,a0),(an1,a1); and (d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1); endmodule //Testbench code for 2-4 Decoder Structural/Gate Level Modelling initial begin // Initialize Inputs a0 = 0;a1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a0=1;a1=0; #100; a0=0;a1=1; #100; a0=1;a1=1; end Output: Verilog 2-4 Decoder Response Other Verilog Programs: Go to Index of Verilog Prog...
VLSI: 2 Bit Magnitude Comparator Dataflow Modelling
module mag_comp2bit( input a0, input a1, input b0, input b1, output p, // p = (a < b) output r, // r = (a > b) output q // q = (a = b) ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule
Comments
Post a Comment