Verilog: 2 to 1 Multiplexer (2-1 MUX) Dataflow Modelling with Testbench Code
Verilog Code for 2 to 1 Multiplexer Dataflow Modelling
module two_to_1_mux(output Y,
input D0, D1, S,
wire T1, T2, Sbar
);assign T1 = D1 & S;
assign T2 = D0 & Sbar;
assign Sbar = ~ S;
assign Y = T1 | T2;
endmodule
//Testbench code for 2-1 MUX (Multiplexer) Dataflow Modelling
initial begin// Initialize Inputs
S = 0; D0 = 0; D1 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100; S = 0;D0 = 0;D1 = 1;
#100; S = 0;D0 = 1;D1 = 0;
#100; S = 0;D0 = 1;D1 = 1;
#100; S = 1;D0 = 0;D1 = 0;
#100; S = 1;D0 = 0;D1 = 1;#100; S = 1;D0 = 1;D1 = 0;
#100; S = 1;D0 = 1;D1 = 1;
end
Xillinx Output:
| 2-1 MUX Dataflow Modelling |
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