Verilog: 4 Bit Counter Behavioral Modelling using If Else Statement

Verilog Code for 4 Bit Counter Behavioral Modelling using If Else Statement

module 4_bit_Count(
    input clock, reset,
    output [3:0]dout
    );
reg [3:0]dout; 
initial dout = 0;
 
always @ (posedge (clock))
   begin 
        if (reset) 
            dout <= 0; 
        else 
            dout <= dout + 1; 
   end 
endmodule

Xillinx Output:

4 Bit Counter Behavioral Modelling Response

 

Also See:

List of Verilog Programs