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Verilog: AND Gate Behavioral Modelling with Testbench Code

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 Verilog Code AND Gate Behavioral Modelling

module AND_GATE ( 
input a, b, 
output out ); 
reg out; 
always @(a or b) 
begin
if(a==1 & b==1) 
out = 1’b1; 
else
out = 1’b0;
endmodule



//test-bench 
initial begin 



a=0; b=0; 
#100; //wait 100ns for global reset to finish 
//add stimulus here 
#100 a=0; b=1; 
#100 a=1; b=0; 
#100 a=1; b=1; 
end



initial begin 
#100 $monitor(“a=%b, b=%b, out=%b”, a, b, out); 
end
endmodule

Xilinx Output:
AND gate Verilog Code Behavioral Modelling
AND Gate Behavioral Response


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